FIG. 1 shows the principal structure of the electronics of a known plasma display panel (PDP).
A video signal is sent to a Digital Board 1 that includes the heart of the PDP processing: the PDP IC controller. This IC takes care of all PDP relevant signal processing and converts video data to sub-field information as usual. Furthermore, the IC is responsible for sending all power signals to the hardware including:                data drivers D1 to D6 of a PDP 2 for sending on the vertical electrodes the bits (1 or 0) for all cells 3 of the current selected lines,        line drivers L1, L2, L3 for selecting lines to be written one after the other and        a common part 4 for generating global signals (in combination with the line drivers) like sustain, erase, priming.        
As shown in FIG. 1, the PDP cell 3 is defined as the crossing point between a vertical electrode coming from a data driver output D1, a horizontal electrode coming from a line driver output L1 and an horizontal electrode coming from the Common electronic 4. The data drivers D1 to D6 are serial to parallel converters as described in connection with FIG. 2. Each data driver Dk (n outputs), receives n sub-field data bits (Cn,t) of line t serially from the PDP IC controller. The input occurs at a frequency defined by clk.
On each starting edge of the enable signal ENA, the n outputs of the driver Dk take the n values stored from the PDP IC. In fact when data Cn,t are send to the input of the driver Dk, the outputs take the values Cn,t−1. The enable signal ENA is included in the addressing signal used to activate the current line t−1. An important point is that the input signals are control logic signals (low voltage) whereas the output signals are power signals (high power ≅60V).
The activity of the driver Dk is defined by two important points:                The activity at the input of the driver: how many changes are occurring during the loading of a driver?        The activity at the output of the driver: how many outputs are changing from one line to another? Furthermore, it is important to notice how these changes are appearing. Indeed if all outputs have the same value and are changing in one time, this is less energy consuming than if each output is different and is changing.        
Based on all these assumptions, a critical test pattern can be defined per driver as illustrated in FIG. 3.
The pattern will introduce an overheating of the driver and above all when the addressing speed is fast (clk and ENA are high frequency signals) like for high-resolution displays. If the driver is overheated a long time (many frames) it can be definitely damaged. Moreover, today, the drivers are bonded on the PDP glass by using glue and it is almost impossible to remove them in order to perform an exchange. Therefore, if a driver has been damaged, the whole panel can be thrown away.
Today, in order to avoid such a problem, there are three possibilities:                A technical one that tries to avoid such an overheating by limiting either the addressing speed (clk and ENA frequencies are low), or the number of sub-fields used per frame.        A coding one that tries to use a specific coding that should reduce the situation depicted in FIG. 3 for a standard picture (reduce the toggling inside a codeword).        A signal-processing one that tries directly to detect critical patterns in order to reduce the number of sub-fields used during addressing.        
A typical real pattern introducing the problem of FIG. 3 is shown in FIG. 4.
The problem is that, even if this pattern is a seldom one and could mainly appear only in case of PC applications, the display should be made robust enough in order not to be destroyed. This needs solutions as those described just before. The problem is that such solutions do not cover all possibilities or all risks. Moreover, some solutions (e.g. coding ones) are limiting the flexibility of the display that can have an impact on the picture quality (e.g. less sub-fields or not optimized coding).